1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device having a semiconductor substrate, a plurality of active elements such as bipolar transistors or Metal-Insulator-Semiconductor (MIS) type transistors formed in the substrate and an isolation region formed on the substrate for isolating the active elements from one another. More particularly, the invention relates to a method for forming a small field isolation structure on a semiconductor substrate for an integrated circuit device.
2. Description of the Prior Art
In a semiconductor integrated circuit device, a plurality of active elements or functional elements formed in a semiconductor substrate are electrically isolated from one another by a field isolation system. The region for the field isolation is comprised of a deep impurity diffusion region, or a thermally grown thick oxide film for conventional devices. The problem with the conventional field isolation structure is that hours of high temperature processing are necessary for the formation of the isolation structure, and fine patterning of the field region is difficult. The latter problem is difficult to solve due to the fact that either impurity diffusion or thermal oxidation for forming the field region is controlled by a diffusion phenomenon and accordingly the width of the region can not be narrower than its depth. In order to solve these problems, insulator isolation structures in which a groove is formed on a surface of a substrate where the isolation region is to be formed and an insulator or semiconductor material is filled therein have been proposed. Such a groove, if formed by a conventional anisotropic etching technique or a dry etching technique, can have a smaller width than its depth. This means that the isolation structure can be miniaturized to achieve a high integration density. Moreover, if a convention chemical vapor deposition (CVD) technique is employed to form the insulator or semiconductor layer for filling the groove, a high temperature as in the impurity diffusion or thermal oxidation process is not required. For these advantages, various processes for forming the insulator isolation structure as explained above have been proposed and tried. However, most of them have not succeeded because of the fatal disadvantage that a polishing or lapping process is necessary to remove the insulator or semiconductor layer on the substrate except in the groove. This lapping process to remove only the insulator or semiconductor layer on the substrate has a poor reproducibility and is difficult to be carried out without damaging the substrate.